`timescale 1ns / 1ps

module SRCA_tb();
reg [3:0] x,y;
reg ci;
wire [4:0] s;
wire cout;

SRCA uut (.x(x), .y(y), .ci(ci), .cout(cout), .s(s));

integer i;
initial begin
ci=1'b0;
for(i=-8; i<=7; i=i+1)
begin
    x=i; y=i; #20;
end
end
endmodule