`timescale 1ns / 1ps
module alu_new (
input [7:0] A,B,
input [1:0] sel,
output reg[7:0] C,
output reg carry
);

reg [8:0] X;

always @ (A,B,sel)

if(sel==2'b00) begin
C = A + B;
if(A>8'b10000000)
carry=1'b1;
else
carry=1'b0;
end


else if(sel==2'b01)
C = A - B;


else if(sel==2'b10) begin
X = A * B;
C = X[7:0];
carry = X[8];
end

else if(sel==2'b11)
C = A / B;


endmodule



`timescale 1ps / 1ps
module tb();
reg[7:0]A,B;
reg[1:0]sel;
wire[7:0]C;
wire carry;
integer i,m;

alu_new uut(.A(A), .B(B), .C(C), .carry(carry), .sel(sel));

initial begin
for (m=0; m<4; m=m+1) begin
sel=m;

for (i=0; i<256; i=i+1) begin
A=i;
B=i;
#10;

end
end

end
endmodule


`timescale 1ns / 1ps
module tb();
reg [6:0] in1, in2;
wire out1;
integer x;

test1 uut(.in1(in1), .in2(in2), .out1(out1));

initial begin
for (x=0; x<256; x=x+1) begin
in1 = x;
in2 = x;
#10;

end
end

endmodule


`timescale 1ns / 1ps
module test1 (
input [6:0] in1, in2,
output reg out1
);

always @ (in1, in2)

if ( (in1%7==0) && (in2%7==0) )
out1 = 1'b1;
else
out1 = 1'b0;
endmodule